1. Field of the Invention
The present invention relates to charge-coupled devices (CCDs) and, in particular, relates to CCDs capable of transferring signal charge while switching multiple driving methods using transfer clocks having different numbers of phases.
2. Description of the Related Art
Mobile phones with a camera function, digital cameras and so on have solid-state image sensing devices with high resolution as high as millions of pixels. Some of the devices have both still-picture photographing and motion photographing functions. Such cameras generally have a display for previewing images to be photographed.
Motion-picture photographing and previewing need high frame rates. However, the time to read signal charge of each pixel from solid-state image sensing devices and the time to process the read signals increase as the number of pixels of the solid-state image sensing devices increases, which makes it difficult to provide high frame rates to the present high-resolution solid-state image sensing devices. In short, although the reading speed and signal processing speed have improved, the present state is not yet enough. Particularly, since CCD image sensors read the signal charge of each pixel sequentially via a horizontal shift register, the horizontal shift register needs to be driven at a clock proportional to the product of the number of pixels and the frame rate, which poses the problems of a decrease in transfer efficiency, an increase in power consumption, and generation of heat.
Motion pictures and preview images do not need resolution as high as that for still pictures. Accordingly, for motion pictures and preview images, the number of charge packets is reduced by addition of the multiple pixels of the image sensing devices, thereby reducing reading time to improve the frame rate.
For example, when photographing still pictures, the charge packets read from a vertical shift register to each bit of the horizontal shift register can be transferred horizontally to the output portion without adding each other. When photographing motion pictures, the charge packets are added into groups of a specified number of packets on the horizontal shift register, and may then be transferred horizontally to the output portion.
FIG. 1 is a schematic plan view of a configuration of a known horizontal shift register. For still-picture photographing, the horizontal shift register horizontally transfers the charge packets read every row from the imaging portion to the output portion by two-phase driving; for motion-picture and previewing-image photographing, the horizontal shift register combines the charge packets read from the imaging portion every three pixels at a time by six-phase driving, and horizontally transfers the combined charge packets to the output portion by three-phase driving.
For the multiple kinds of driving of different numbers of phases, the horizontal shift register is constructed so as to be driven by six-phase clock signals, in which six clock-signal lines are provided along a channel region 2 of the horizontal shift register.
Transfer electrodes 4-1 to 4-6 are disposed at regular intervals in this order on the channel region 2 along the direction in which charge is transferred. Outside the channel region 2, a set of clock signal lines 6 is disposed to provide clocks to the group of transfer electrodes. For two-phase driving, three-phase driving, and six-phase driving, the one set of clock signal lines 6 is composed of six clock signal lines, which are arranged in parallel along the channel region 2.
The transfer electrodes 4-1 to 4-6 connect to the different clock signal lines 6 via a contact 8. Here, a clock signal line 6 connected to a transfer electrode 4-i (i=1 to 6) is indicated by symbol “PHi”. With known structures, clock signal lines PH1 to PH6 are disposed in sequence from the side adjacent to the channel region 2 in accordance with the order of the transfer electrodes 4-1 to 4-6.
At six-phase driving, the transfer electrodes 4-1 to 4-6 are switched between on and off in sequence. In this case, the clock signal lines PH1 to PH6 are supplied with six-phase clock signals φ1 to φ6 in different phases. At two-phase driving, the transfer electrodes 4 are driven in a manner such that the odd-numbered transfer electrodes 4 come in phase, and the even-numbered transfer electrodes 4 come in phase. Specifically, clock signal lines PH1, PH3, and PH5 are supplied with a common clock signal φ1′, and clock signal lines PH2, PH4, and PH6 are supplied with a common clock signal φ2′. At three-phase driving, the transfer electrodes 4 are driven so as to be in phase every three lines. Specifically, clock signal lines PH1 and PH4 are supplied with a common clock signal φ1″, clock signal lines PH2 and PH5 are supplied with a common clock signal φ2″, and clock signal lines PH3 and PH6 are supplied with a common clock signal φ3″.
With the above structure, the clock signal lines PH1 to PH6 are disposed contiguously in parallel, thus resulting in possible crosstalk due to the capacitive coupling among them. The crosstalk among the clock signal lines may decrease the transfer efficiency of the CCD shift register. The effect of the crosstalk increases particularly between adjacent clock signal lines. Accordingly, with the structure of FIG. 1 in which clock signal lines corresponding to adjacent transfer electrodes are disposed next to each other, at the operation of transferring charge packets between the transfer electrodes, crosstalk tends to occur. The crosstalk at that case acts to weaken the fringe electric field between adjacent transfer electrodes, which may decrease the transfer efficiency.